Computer system having peer-to-peer bus bridges and shadow configuration registers

ABSTRACT

A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.

TECHNICAL FIELD

[0001] The present invention relates to computer systems, and moreparticularly, to a method of configuring a computer system with a peerto peer arrangement of computer buses.

BACKGROUND OF THE INVENTION

[0002] A computer system typically includes a central processing unit(CPU) coupled by communication pathways known as computer buses tovarious computer components, such as memory, input devices, and a videomonitor. To enable the CPU to communicate with the computer components,the computer components must be configured to communicate in anorganized manner. Typically, each computer device includes a set ofconfiguration registers that store configuration data, such as dataidentifying the type and capabilities of the computer device. Some ofthe configuration data, such as the device type, is provided with thecomputer device by the device manufacturer. In addition, the CPUtypically provides each computer device with additional configurationdata that defines how the computer devices will interact with each otherand with the CPU.

[0003] Virtually all computer devices utilize some memory address space,input/output (I/O) address space or both. When the computer system isturned on, the computer system must be configured so that each computerdevice's I/O and memory functions occupy mutually exclusive addressranges. After determining how much memory and I/O space a computerdevice requires, the CPU assigns the computer device I/O and/or memoryaddress ranges that do not conflict with I/O and memory address rangesassigned to any other computer device of the computer system.

[0004] A block diagram of a typical prior art computer system 10,employing a hierarchical architecture of computer buses, is shown inFIG. 1. The computer system 10 includes a computer processor 12 coupledby a host bus 14 to a read-only memory (ROM) device 16, a host-PCIbridge 18 and a memory controller 20 coupled to a system memory module22. Coupled to the host-PCI bridge 18 by a first Peripheral ComponentInterconnect (PCI) bus 24 are a PCI-ISA bridge 26, first PCI-PCI bridge28, and second PCI-PCI bridge 30. The PCI-ISA bridge 26 couples thefirst PCI bus 24 to an industry standard architecture (ISA) bus 32 whichis coupled to an input device 34 and a floppy drive 36. The firstPCI-PCI bridge 28 couples the first PCI bus 24 to a second PCI bus 38,which is coupled to a video controller 40 and a hard drive 42. Thesecond PCI-PCI bridge 30 couples the first PCI bus 24 to a third PCI bus44, which is coupled to a network adapter 46 and a fax-modem 48.

[0005] When the computer system 10 is turned on, the processor 12configures the computer system 10 based on computer instructions ofbasic input/output system (BIOS) routines 50 stored in the ROM device16. The BIOS routines 50 are hardware-specific in that the manufacturerof the computer system 10 designs the BIOS routines specifically for theparticular implementation of the computer system 10 being sold. As aresult, any configuration of computer buses and computer devices can beemployed without limiting the ability of the computer system to beconfigured by the BIOS routines 50. The BIOS is the only agentresponsible for configuring the PCI-PCI bridges, because interrupts foreach bus must be routed by the BIOS.

[0006] One drawback of configuring the computer system 10 using thehardware-specific BIOS routines 50 is that only computer devicesdesigned according to the configuration rules implemented by the BIOSroutines 50 can be added to the computer system 10. The PCIspecification is being modified to allow the interrupt routing to beperformed by the computer's operating system, such as Microsoft Windows™and Microsoft Windows NT™. As a result, the operating system must beallowed to configure PCI-PCI bridges using the configuration formatdefined by the “PCI-PCI Bridge Architecture Specification” issued by thePCI Special Interest Group on Apr. 5, 1994, which is incorporated hereinby reference. Such changes to the PCI specification may reducecompatibility problems, but do not provide the operating system with amethod of configuring computer systems that do not employ thetraditional hierarchical architecture of the computer system 10 shown inFIG. 1.

SUMMARY OF THE INVENTION

[0007] An embodiment of the present invention is directed to a method ofconfiguring a computer system having a processor coupled by a host busto first and second bus devices. The processor transmits on the host busone or more configuration write commands that include configuration datarepresenting a range of addresses assigned to the second bus device. Theconfiguration data is stored on the first and second bus devices. Theprocessor transmits on the host bus a transaction request directed to anaddress within a range of addresses assigned to the second bus device.The first bus device determines that it should not transmit a responseto the transaction request based on the configuration data stored in thefirst bus device. The first bus device may include a set ofconfiguration registers for storing configuration data regarding thefirst bus device and a set of shadow configuration registers for storingconfiguration data regarding the second bus device.

[0008] Another aspect of the invention is directed to a method ofconfiguring first and second PCI bridges in a computer system having aprocessor coupled by a host bus to the PCI bridges. The first PCI bridgecouples a first PCI bus to the host bus and the second PCI bridgecouples a second PCI bus to the host bus. The processor transmits on thehost bus a configuration command that includes a device identifier thatidentifies the second PCI bridge and a bus identifier that identifiesthe first PCI bus. Upon receiving the configuration command from thehost bus, the second PCI bridge responds to the configuration commandsuch that the second PCI bridge appears to be directly coupled to thefirst PCI bus when the second PCI bridge is actually indirectly coupledto the first PCI bus via the host bus and the first PCI bridge.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a block diagram of a prior art computer system employinga hierarchical arrangement of computer buses.

[0010]FIG. 2 is a block diagram of a computer system employing a peer topeer arrangement of computer buses according to the present invention.

[0011]FIG. 3 is a block diagram of a first PCI-PCI bridge employed inthe computer system shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0012] A block diagram of a computer system 60 that may operate inaccordance with an embodiment of the present invention is shown in FIG.2. In contrast to the hierarchical bus architecture employed in theprior art computer system 10 shown in FIG. 1, the computer system 60employs a flatter, peer to peer arrangement of computer buses. That is,rather than employing a single host-PCI bridge 18 like the prior artcomputer system 10, the computer system 60 includes a processor 62coupled by a host bus 64 to first, second and third peer to peer PCIbridges 66, 68, 70. The first PCI bridge 66 includes a memory controller72 coupled to a system memory 74 which may be implemented using any typeof dynamic random access memory (DRAM). The system memory 74 stores anoperating system 76 that controls how the processor 62 interacts withthe hardware and software of the computer system 60.

[0013] The first PCI bridge 66 couples the host bus 64 to a first PCIbus 82 which is coupled to a PCI-ISA bridge 84. The PCI-ISA bridge 84couples the first PCI bus 82 to an ISA bus 86, which is coupled to afloppy drive 88 and an input device 90, such as a keyboard, mouse, ormicrophone that enables a user to input information into the computersystem 60. The second PCI bridge 68 couples the host bus 64 to a secondPCI bus 92, which is coupled to a hard drive 94 and a video controller96. The video controller 96 is coupled to a video monitor 98 thatenables information to be output to the user. The third PCI bridge 70couples the host bus 64 to a third PCI bus 100, which is coupled to afax-modem 102 and a network adapter 104 that enables the computer systemto be part of a network, such as a local area network (LAN) or anIntranet.

[0014] The PCI bridges 66-70 and the PCI-ISA bridge 84 includeconfiguration registers 106, 108, 110, 112, respectively. Each of theconfiguration registers 106-112 stores configuration data for itsrespective bridge 66-70, 84. Among the configuration data stored in theconfiguration registers 106-112 are memory and I/O address rangesassigned to the respective bridges 66-70, 84 by the processor 62, asdiscussed in more detail below. The address range assigned to the firstPCI bridge 66 includes a memory address range assigned to the systemmemory 74. Each of the computer devices 88-90, 94-96, 102-104 alsoincludes configuration registers, but further discussion of thoseconfiguration registers is well known in the art and is being omitted toavoid unnecessarily obscuring the present invention.

[0015] The peer to peer architecture of the PCI bridges 66-70 ofcomputer system 60 shown in FIG. 2 has been found to perform moreefficiently than the hierarchical architecture of the computer system 10shown in FIG. 1. That is because all of the computer components 24-48downstream of the host-PCI bridge 18 in the system of FIG. 1 mustcommunicate with the processor 12 via the single host-PCI bridge 18 inthe computer system 10 while the computer system 60 of FIG. 2 includesthree peer to peer PCI bridges 66-70 that enable the computer components82-104 to communicate with the processor 62. In the prior art computersystem 10, the PCI-ISA bridge 26, first PCI-PCI bridge 28, and secondPCI-PCI bridge 30 all have to compete for access to the first PCI bus 24and the host-PCI bridge 18 before transactions from the bridges 26-30can even compete for the host bus 14. In contrast, in the disclosedembodiment of the inventive method, all three peer to peer PCI bridges66-70 compete directly for the host bus 64 without having to go througha separate host-PCI bridge.

[0016] One problem with the peer to peer arrangement employed by thecomputer system 60 is that a way must be found to forward transactionrequests from the host bus 64 to the PCI-ISA bridge 84 via the first PCIbridge 66 and first PCI bus 82. In the prior art computer system 10 ofFIG. 1, the host-PCI bridge 18 simply forwards all transaction requestsnot claimed by the memory controller 20 to the first PCI bus 24 and thetransactions are claimed by either the PCI-ISA bridge 26 or one of thePCI-PCI bridges 28, 30. However, in the computer system 60, the PCI-ISAbridge 84 is not directly connected to the host bus 64 like the PCIbridges 66-70. As a result, the first PCI bridge 66 needs to be providedwith a way to claim transaction requests on the host bus 64 that areintended for the PCI-ISA bridge 84.

[0017] In order to enable transaction requests to be forwarded to thePCI-ISA bridge 85, the first PCI bridge 66 includes a set of shadowconfiguration registers 114. The shadow configuration registers 114 aredesigned to store at least a portion of the configuration data stored inthe configuration registers 108, 110 of the second and third PCI bridges68, 70, respectively. In particular, the shadow configuration registers114 store the configuration data that reflects the memory and I/Oaddress ranges assigned to the second and third PCI bridges 68, 70.Knowledge of the address ranges assigned to the second and third PCIbridges 68, 70 enables the first PCI bridge 66 to claim all transactionrequests on the host bus 64 that do not include addresses within theranges assigned to the second and third PCI bridges 68, 70. The firstPCI bridge 66 forwards such transaction requests on the first PCI bus 82to the PCI-ISA bridge 84 for further processing.

[0018] Assigning non-conflicting memory and I/O address ranges to thePCI bridges 66-70 would be relatively simple if hardware-specific BIOSroutines were employed to configure the computer system 60. Such BIOSroutines can be programmed with information indicating that the computersystem 60 is employing a peer to peer arrangement rather than thehierarchical architecture employed by the prior art computer system 10.However, when the operating system 74 is responsible for configuring thecomputer system 60, the operating system 74 expects to be configuring ahierarchical architecture with a single host-PCI bridge like the priorart computer system 10.

[0019] In the prior art method of operating the computer system 10 ofFIG. 1, the processor 12 configures the computer system 10 in severalsteps based on computer instructions from the BIOS 50. The processor 12issues configuration read requests to determine what computer devicesare being employed in the computer system 10.

[0020] Each of the buses 14, 24, 32, 38, 44 is able to be directlycoupled to a predetermined number of computer devices in predeterminednumbered positions. For example, a PCI bus, such as the PCI buses 24,38, 44 has 32 numbered positions for directly connecting 32 possiblecomputer devices. The configuration read requests sequentially ask thecomputer device (if there is one) in each numbered position of each busto identify relevant information about the computer device, includinghow much memory and I/O address space is desired by the computer device.These configuration read requests are directed to the configurationregisters in each of the computer devices 26-30, 34-36, 40-42, 46-48.Along the way, the processor 12 assigns a bus number to each of the PCIbuses 24, 38, 44, beginning with assigning PCI bus number zero to thefirst PCI bus 24.

[0021] After determining how much memory and I/O address space each ofthe computer devices requests, the processor 12 issues writeconfiguration requests to assign appropriate memory and I/O addressranges to each of the computer devices. The processor 12 issues a writeconfiguration request by using two I/O registers of the host-PCI bus 18as an address/data pair. In particular, the processor 12 writes to aconfiguration address register an address that includes a bus number,device number, function number (or a multi-function device), and aregister number for the device function. The bus number indicates thebus to which the intended computer device is directly connected andwhich is between the device and the host bus 14. The processor alsowrites the desired configuration data into an I/O register known as adata register. For example, to give the first PCI-PCI bridge 28 aminimum memory address of a memory address range, the processor 12writes to the configuration address register the bus number of the firstPCI bus 24 and the device number for the first PCI-PCI bridge and writesto the data register the minimum address value. The host-PCI bridge 18recognizes that the bus number written to the configuration addressregister indicates the first PCI bus 24 which is directly coupled to thehost-PCI bridge 18, so the host-PCI bridge 18 forwards the writeconfiguration request on the first PCI bus 24. The first PCI-PCI bridge28 recognizes that the write configuration request is directed toitself, and copies the minimum memory address into one of itsconfiguration registers.

[0022] Given that all memory requests on the host bus 14 are directed toeither the memory controller 20 or the host-PCI bridge 18, the host-PCIbridge 18 needn't be given a specific memory address range. Instead, thehost-PCI bridge 18 is given information indicating the limit of thesystem addresses granted to the system memory 22, such that the host-PCIbridge 18 knows to respond to all memory requests that have memoryaddresses outside of the range given to the system memory 22. Thehost-PCI bridge 18 forwards such memory requests on the first PCI bus24.

[0023] The method of configuring the prior art computer system 10 wouldbe substantially identical if the configuration responsibility switchedfrom the BIOS 50 to the operating system of the computer system 10. Theonly difference would be that the processor 12 would issue theconfiguration read and write requests based on instructions from theoperating system rather than from the BIOS 50. The processor 12 wouldstill issue configuration requests to the host-PCI bridge 18 which wouldforward the configuration requests on the first PCI bus 24 in order toprogram the configuration registers of the PCI-ISA bridge 26, firstPCI-PCI bridge 28, and second PCI-PCI bridge 30 and the computer devices34-36, 40-42, 46-48 subordinate to those bridges 26-30.

[0024] However, in the computer system 60, there is no single host-PCIbridge through which the configuration requests can be routed. The PCIbridge specification to be implemented by the operating system 74 doesnot account for the more efficient peer to peer bus arrangements.Consequently, in order to physically implement the peer to peer PCIbridges 66-70 in a computer system that is configured by the operatingsystem 74, the PCI bridges 66-70 must appear logically as a traditionalhierarchical arrangement of buses to the operating system 74.

[0025] Based on the configuration instructions from the operating system74, the processor 62 assigns memory and I/O address ranges to thecomputer devices 70, 84, 88-90, 94-96, 102-104 as if the computer system60 were employing a traditional hierarchical arrangement. The operatingsystem 76 views the computer system 60 logically as the first PCI bridge66 being a host-PCI bridge coupling the host bus 64 to the first PCI bus82 (which it labels PCI bus zero) that is coupled directly to each ofthe second and third PCI bridges 68-70. As such, the operating system 76does not assign a specific memory address range to the first PCI bridge66. Instead, the first PCI bridge 66 is given information indicating thelimit of the system memory addresses assigned to the system memory 74,such that the first PCI bridge 66 knows which memory requests are notdirected to the system memory 14.

[0026] Of course, in reality, the first PCI bridge 66 does not couplethe second and third PCI bridges 68-70 to the host bus 64 because thehierarchical arrangement is not being employed. However, in order tologically appear to the operating system 74 as part of a hierarchicalarrangement, the PCI bridges 66-70 respond to the configuration readrequests as if the second and third PCI bridges 68-70 were coupled tothe host bus 64 by the first PCI bus 82 and the first PCI bridge 66.Thus, the first PCI bridge 66 passes all configuration read requeststhrough to the first PCI bus 82. The second PCI bridge 68 may respond toconfiguration read requests directed to position number zero of thefirst PCI bus 82, the third PCI bridge 70 may respond to configurationread requests directed to position number 1 of the first PCI bus 82, andthe PCI-ISA bridge 84 may respond to configuration read requestsdirected to position number 2 of the first PCI bus 82. It will beappreciated that the position number assigned to each of the second andthird PCI bridges 68-70 will depend on the position of those PCI bridges68-70 on the host bus 64. In its responses to the configuration readrequests, the PCI bridges 68-70 inform the processor 62 that the devicetypes are PCI bridges. The operating system 74 will query each of thedevices 84, 94-96, 102-104 on each PCI bus below each of the PCI bridges66-70 to determine how much memory and I/O space is required by eachdevice. Using this information, the operating system 74 will determinethe amount of memory and I/O space required for each PCI bridge 66-70 bysumming up the total requirements for all the devices below that bridge.

[0027] Upon learning that the PCI bridges 66-70 are PCI bridges, theprocessor 62 knows that the PCI bridges 66-70 are coupled to the PCIbuses 82, 92, 100 because all PCI bridges are coupled to PCI buses. Theprocessor 62 responds by assigning bus numbers 0, 1, and 2, to the PCIbuses 82, 92, 100, respectively. The processor 62 then issuesconfiguration read requests to determine what computer devices arecoupled to the PCI buses 82, 92, 100. The configuration read requestswill include the bus numbers, so the PCI bridges 66-70 will know thatthe configuration read requests are intended for the PCI buses 82, 92,100. As a result, the PCI bridges forward the configuration readrequests to their respective PCI buses 82, 92, 100. The computer devices84, 94-96, 102-104 respond to the configuration read requests withinformation regarding their device types and address space requirements.

[0028] After determining which numbered positions of each of the buses64, 82, 86, 92, 100 are occupied by computer devices, the processor 62issues configuration write requests to the computer devices. Theconfiguration write requests include memory and I/O address rangesassigned to each of the computer devices that requested such addressranges in response to the configuration read requests. The processor 62creates an address translation table that lists the memory and I/Oaddress ranges assigned to each of the computer devices coupled to eachof the computer buses 64, 82, 86, 92, 100.

[0029] The first PCI bridge 66 monitors all of the configuration writerequests transmitted on the host bus 64 to determine which addressranges are being assigned to the second and third PCI bridges 68-70. Inaddition, the first PCI bridge 66 stores in the shadow configurationregisters 114 the address ranges assigned to the second and third PCIbridges 68-70.

[0030] A block diagram of the first PCI bridge 66 is shown in FIG. 3.The configuration registers 106 for storing configuration data for thefirst PCI bridge 66 include a device identifier register 106A, a primarybus register 106B, a secondary bus register 106C, an I/O limit register106D, and an I/O base register 106E. The device identifier register 106Astores a predetermined device identifier that identifies the first PCIbridge's device type, that is, identifies that it is a PCI bridge. Thesystem manufacturer loads the appropriate device identifier in thedevice identifier register 106A which is read by the processor 62 usinga configuration read request as discussed above. The primary bus numberregister 106B stores the bus number that is immediately upstream (closerto the processor 62) of the first PCI bridge 66 and the secondary busregister number 106C stores the bus number of the immediately downstream(away from the processor 62) bus with respect to the first PCI bridge66. In reality, the host bus 64 is the bus that is immediately upstreamof the first PCI bridge 66, but because the operating system 76 “thinks”that a virtual PCI bus 0 exists between the host bus 64 and the firstPCI bridge 66, the primary bus register 106B stores PCI bus number 0.The I/O limit register 106D and the I/O base register 106E store theupper and lower values, respectively, of the I/O address range assignedto the first PCI bridge 66.

[0031] It should be appreciated that the PCI specification also refersto several other registers (not shown) that should be included in theconfiguration register file 106, including a command register, secondaryand subordinate bus number registers, prefetchable memory base/limitregisters, and a bridge control register. The function of each of theseregisters is discussed in the “PCI To PCI Bridge ArchitectureSpecification” discussed above. However, a detailed discussion of theseregisters is not necessary for an understanding of the invention, andthus, is being omitted for simplicity.

[0032] The shadow registers 114 of the first PCI bridge 66 include afirst set of shadow configuration registers 114′ and a second set ofshadow configuration registers 114″ for the address ranges assigned tothe second and third PCI bridges 68, 70, respectively. The first set ofshadow configuration registers 114′ include an I/O limit register 114A′,and I/O base register 114B′, a memory limit register 114C′, and a memorybase register 114D′ for storing the I/O and memory address rangesassigned to the second PCI bridge 68. The second set of shadowconfiguration registers 114″ includes an I/O limit register 114A″, anI/O base register 114B″, a memory limit register 114C″, and a memorybase register 114D″ for storing the I/O and memory address rangesassigned to the third PCI bridge 70. The shadow configuration registers114 may also include other configuration registers (not shown), such asthe command, secondary subordinate bus number, prefetchable memorybase/limit, and bridge control registers discussed above.

[0033] The first PCI bridge 66 also includes primary and secondarytarget interfaces 116, 118 and primary and secondary master interfaces120, 122. The primary target interface 116 is coupled between the hostbus 64 and the secondary master interface 122 which is coupled to thefirst PCI bus 82. The primary target interface 116 and the secondarymaster interface 122 execute transactions directed to the first PCI bus82 from the host bus 64. The secondary target interface 118 is coupledbetween the first PCI bus 82 and the primary master interface 120 whichis coupled to the host bus 64. The secondary target interface 118 andthe primary master interface 120 execute transactions directed tocomputer devices on the host bus 64 from computer devices coupled to thefirst PCI bus 82.

[0034] The primary target interface 116 is responsible for monitoringthe host bus 64 for configuration requests directed to any of the PCIbridges 66-70. As such, the primary target interface 116 responds toconfiguration read requests directed to the first PCI bridge 66 byreading the requested data from the configuration registers 106 andtransmitting the configuration data to the processor 62 via the host bus64. In addition, the primary target interface 116 responds toconfiguration write requests directed to any of the PCI bridges 66-70 bywriting the configuration data in the configuration write requests tothe appropriate one of the configuration registers 106, 114 depending onwhich of the PCI bridges the configuration write requests are directed.

[0035] After all of the configuration registers of the computer devices66-70, 84, 88-90, 94-96, 102-104 in the computer system 60 areconfigured, the computer devices are ready to process computertransactions. For example, if a transaction request is directed to amemory address within the range of memory addresses assigned to thesecond PCI bridge 68, then the second PCI bridge determines from itsconfiguration register 108 that it should respond to the transactionrequest. The second PCI bridge 68 responds by forwarding the transactionrequest on the second PCI bus 92 so that either the hard drive 94 orvideo controller 96 can execute the transaction request depending onwhich of them was assigned the address included in the transactionrequest. In addition, the first PCI bridge 66 determines from its shadowconfiguration registers 114′ that the first PCI bridge 66 should notrespond to the transaction request.

[0036] If the processor 62 issues a transaction request directed to thefloppy drive 88, then the first PCI bridge 66 must claim the transactionrequest off of the host bus 64. The first PCI bridge 66 will compare theaddress included in the transaction request with the memory addressrange assigned to the system memory 74 and with the address ranges inthe shadow configuration registers 114 to determine whether the addressin the transaction request is within the address ranges assigned to thesecond and third PCI bridges 68, 70. Given that the floppy drive 88 isnot coupled to the host bus 64 by either of the second and third PCIbridges 68, 70, the first PCI bridge 66 determines that the transactionrequest is not directed to either of the second and third PCI bridges68, 70. In response, the first PCI bridge 66 claims the transactionrequest from the host bus 64 and forwards the transaction request on thefirst PCI bus 82. The PCI-ISA bridge 84 claims the transaction requestfrom the first PCI bus 82 and forwards the transaction request to thefloppy drive 88 via the ISA bus 86.

[0037] Based on the foregoing discussion, it will be appreciated thatthe embodiments of the present invention enables a peer to peerarrangement of computer buses to be configured by an operating systemdesigned to configure only hierarchical arrangements of computer buses.As such, the advantages of the peer to peer arrangement are obtainedwithout requiring hardware-specific BIOS routines to configure thecomputer system. The embodiments discussed above employ shadowconfiguration registers to make the physical peer to peer arrangementlogically appear to the operating system as a traditional hierarchicalarrangement.

[0038] It should be understood that even though numerous advantages ofthe present invention have been set forth in the foregoing description,the above disclosure is illustrative only. Changes may be made in detailand yet remain within the broad principles of the present invention.

1. A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising: transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device; storing the configuration data on the first and second bus devices; transmitting from the processor on the host bus a transaction request directed to an address with the range of addresses assigned to the second bus device; and determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.
 2. The method of claim 1 wherein the first and second bus devices are respective first and second PCI bridges that couple the host bus to respective first and second PCI buses.
 3. The method of claim 2 wherein the act of transmitting the one or more configuration write commands includes transmitting one or more PCI type 1 configuration write commands on the host bus and the method further comprises: determining that the one or more PCI type 1 configuration write commands are intended for the second PCI bridge, and in response, storing the configuration data in the first and second PCI bridges without converting the PCI type 1 configuration write commands into PCI type 0 configuration write commands.
 4. The method of claim 1 wherein the act of transmitting the one or more configuration write commands includes transmitting the one or more configuration write commands from the processor based on instructions of an operating system.
 5. The method of claim 1, further comprising: determining, based on the configuration data stored in the second bus device, that the second bus device should transmit a response to the transaction request; and transmitting a response to the transaction request using the second bus device.
 6. The method of claim 1 wherein the act of storing the configuration data in the first and second bus devices includes storing a range of memory addresses and a range of I/O addresses.
 7. The method of claim 1 wherein the computer system includes a third bus device coupled to the host bus, the method further comprising: transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the third bus device; and storing on the first and third bus devices the configuration data representing a range of addresses assigned to the third bus device.
 8. A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices, the method comprising: transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the second bus device; capturing the configuration data from the host bus in the first and second bus devices; storing the configuration data in one or more configuration registers of the second bus device; and storing the configuration data in one or more shadow configuration registers of the first bus.
 9. The method of claim 8, further comprising: transmitting from the processor on the host bus a transaction request directed to an address with the range of addresses assigned to the second bus device; and determining, based on the configuration data stored in the first bus device, that the first bus device should not transmit a response to the transaction request.
 10. The method of claim 8 wherein the first and second bus devices are respective first and second PCI bridges that couple the host bus to respective first and second PCI buses.
 11. The method of claim 10 wherein the act of transmitting the one or more configuration write commands includes transmitting one or more PCI type 1 configuration write commands on the host bus, the capturing act includes determining that the one or more PCI type 1 configuration write commands are intended for the second PCI bridge, and the storing acts include storing the configuration data in the first and second PCI bridges without converting the PCI type 1 configuration write commands into PCI type 0 configuration write commands.
 12. The method of claim 8 wherein the act of transmitting the one or more configuration write commands includes transmitting the one or more configuration write commands from the processor based on instructions of an operating system.
 13. The method of claim 8, further comprising: transmitting from the processor on the host bus a transaction request directed to an address with the range of addresses assigned to the second bus device; determining, based on the configuration data stored in the second bus device, that the second bus device should transmit a response to the transaction request; and transmitting a response to the transaction request using the second bus device.
 14. The method of claim 8 wherein the acts of storing the configuration data in the first and second bus devices includes storing a range of memory addresses and a range of I/O addresses.
 15. The method of claim 8 wherein the computer system includes a third bus device coupled to the host bus, the method further comprising: transmitting one or more configuration write commands on the host bus from the processor, the one or more configuration write commands including configuration data representing a range of addresses assigned to the third bus device; and storing on the first and third bus devices the configuration data representing a range of addresses assigned to the third bus device.
 16. A method of configuring first and second PCI bridges in a computer system having a processor coupled by a host bus to the PCI bridges, the first PCI bridge coupling a first PCI bus to the host bus and the second PCI bridge coupling a second PCI bus to the host bus, the method comprising: transmitting from the processor on the host bus a configuration command that includes a device identifier that identifies the second PCI bridge and a bus identifier that identifies the first PCI bus; receiving the configuration command from the host bus at the second PCI bridge; and responding to the configuration command using the second PCI bridge such that the second PCI bridge appears to the processor to be directly coupled to the first PCI bus when the second PCI bridge is actually indirectly coupled to the PCI bus via the host bus and the first PCI bridge.
 17. The method of claim 16 wherein the configuration command is a configuration write command that includes configuration data, the method further including: storing the configuration data in a configuration register file of the second PCI bridge; and storing the configuration data in a shadow configuration register file of the first PCI bridge.
 18. The method of claim 17 wherein the configuration data includes a base address that, together with a limit address stored in the first and second PCI bridges, defines an address range assigned to the second PCI bridge, the method further comprising: transmitting from the processor on the host bus a transaction request directed to an address within the address range assigned to the second PCI bridge; and determining, based on the configuration data stored in the first PCI bridge, that the first PCI bridge should not forward the transaction request to the first PCI bus coupled to the first PCI bridge.
 19. The method of claim 17 wherein the configuration data includes a base address that, together with a limit address stored in the first and second PCI bridges, defines an address range assigned to the second PCI bridge, the method further comprising: transmitting from the processor on the host bus a transaction request directed to an address not within the address range assigned to the second PCI bridge; and determining, based on the configuration data stored in the first PCI bridge, that the first PCI bridge should forward the transaction request to the first PCI bus coupled to the first PCI bridge.
 20. The method of claim 17, further comprising: determining, based on the configuration data stored in the second PCI bridge, that the second PCI bridge should transmit a response to the transaction request; and transmitting a response to the transaction request using the second PCI bridge.
 21. The method of claim 16 wherein the act of transmitting the configuration command includes transmitting the configuration command from the processor based on instructions of an operating system. 